1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a semiconductor device with a spacer etch block cap, and the resulting semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In general, as a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be “device-level” contacts or simply “contacts” within the industry, as they contact the “device” that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.
In some cases, the second, upper end of the contact structure may be connected to a contact region of another semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. These local interconnect structures typically connect circuit elements, e.g., transistors, resistors, etc., that are formed on different spaced-apart active regions that are electrically isolated from one another. Such local interconnect structures are generally line-type structures that are formed in the interlayer dielectric material below the metallization system of the product.
As device dimensions have decreased, e.g., transistors with gate lengths of 50 nm and less, the contact elements in the contact level have to be provided with critical dimensions on the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
For this reason, contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, at least the sidewall spacers of the gate electrode structures are used as etch masks for selectively removing the silicon dioxide material in order to expose the contact regions of the transistors, thereby providing self-aligned trenches which are substantially laterally delineated by the spacer structures of the gate electrode structures. Consequently, a corresponding lithography process only needs to define a global contact opening above an active region, wherein the contact trenches then result from the selective etch process using the spacer structures, i.e., the portions exposed by the global contact opening, as an etch mask. Thereafter, an appropriate contact material, such as tungsten and the like, may be filled into the contact trenches.
However, the aforementioned process of forming self-aligned contacts results in an undesirable loss of at least portions of the spacer materials that protect the conductive gate electrode, as will be explained with reference to FIGS. 1A-1B. FIG. 1A schematically illustrates a cross-sectional view of an integrated circuit product 10 at an advanced manufacturing stage. As illustrated, the product 10 comprises a plurality of illustrative gate structures 11 that are formed above a substrate 12, such as a silicon substrate. The gate structures 11 are comprised of an illustrative gate insulation layer 13 and an illustrative gate electrode 14. An illustrative gate cap layer 16 and sidewall spacers 18 encapsulate and protect the gate structures 11. The gate cap layer 16 and sidewall spacers 18 are typically made of silicon nitride. Also depicted in FIG. 1A are a plurality of raised source/drain regions 20 and a layer of insulating material 22, e.g., silicon dioxide. FIG. 1B depicts the product 10 after an opening 24 has been formed in the layer of insulating material 22 for a self-aligned contact. Although the contact etch process performed to form the opening 24 is primarily directed at removing the desired portions of the layer of insulating material 22, portions of the protective gate cap layer 16 and the protective sidewall spacers 18 get consumed during the contact etch process, as simplistically depicted in the dashed regions 26. Given that the cap layer 16 and the spacers 18 are attacked in the contact etch process, the thickness of these protective materials must be sufficient such that, even after the contact etch process is completed, there remains sufficient material to protect the gate structures 11. Accordingly, device manufacturers tend to make the cap layers 16 and spacers 18 having an additional thickness that may otherwise not be required but for the consumption of the cap layers 16 and the spacers 18 during the contact etch process. In turn, increasing the thickness of such structures, i.e., increasing the thickness of the gate cap layers 16, causes other problems, such as increasing the aspect ratio of the contact opening 24 due to the increased height, increasing the initial gate height, which makes the gate etching and spacer etching processes more difficult, etc.
The present disclosure is directed to various methods of forming a semiconductor device with a spacer etch block cap, and the resulting semiconductor device, that may avoid, or at least reduce, the effects of one or more of the problems identified above.